Introduction
Memory latency indicates the time the system waits for memory response before entering the data access operation ready state. It is usually represented by 4 consecutive Arabic numerals, such as "3-4 -4-8", generally speaking, the later the four numbers are, the larger the value, the smaller the four numbers, the better the memory performance. Since there is no lower latency than 2-2-2-5, the International Memory Standards Organization believes that 0 or 1 latency cannot be achieved with current dynamic memory technology. But it is not that the smaller the delay, the higher the memory performance, because the four values of CL-tRCD-tRP-tRAS are used in conjunction, and the degree of mutual influence is very large, and the performance is not the worst when the value is the largest, so it is more reasonable The ratio of the parameters is very important.
The first number is the most important. It represents the delay (CASLatency) between the registered read command and the first output data, that is, the CL value, and the unit is clock cycle. This is the response time of the vertical address pulse.
The second number represents the delay time from the memory row address to the column address (RAStoCASDelay), which is tRCD.
The third number represents the precharge time (RASPrecharge) from the memory row address controller, which is tRP. Refers to the interval time from the end of a row access to the restart of the memory.
The fourth number represents the activation time of the memory row address controller Act-to-PrechargePrechargeDelay (tRAS),
Detailed explanation
There is a special memory delay time The term is "Latency". To understand the delay vividly, we might as well regard the memory as an array of stored data, or an EXCEL table. To determine the location of each data, each data is marked with a row and column sort number. After determining the row, The data is unique after the column number. When the memory is working, before reading or writing certain data, the memory control chip will first transmit the row address of the data, this RAS signal (RowAddressStrobe, row address signal) is activated, and before converting to the row data, it needs After several execution cycles, then the CAS signal (ColumnAddressStrobe, column address signal) is activated. The several execution cycles between the RAS signal and the CAS signal are the RAS-to-CAS delay time. It also takes several execution cycles after the CAS signal is executed. This execution cycle is about 2 to 3 cycles when using standard PC133 SDRAM, while DDRRAM is 4 to 5 cycles. In DDR, the real CAS delay time is 2 to 2.5 execution cycles. The time of RAS-to-CAS depends on the technology, it is about 5 to 7 cycles, which is also the basic factor of delay.
The memory with lower CL setting has a higher advantage, which can be expressed from the total delay time. The total delay time of the memory has a calculation formula, the total delay time = system clock cycle × CL mode number + access time (tAC). First, let’s understand the concept of access time (tAC). tAC is the abbreviation of AccessTimefromCLK, which refers to the maximum number of input clocks when the maximum CAS delay occurs. It is measured in nanoseconds. It is a completely different concept from the memory clock cycle. They are all measured in nanoseconds. The access time (tAC) represents the time to read and write, and the clock frequency represents the speed of the memory.
Operation method
Take an example to calculate the total delay time. For example, a DDR333 memory has an access time of 6ns, and its memory clock cycle is 6ns (DDR memory clock cycle= 1X2/memory frequency, if the DDR400 memory frequency is 400, the clock cycle can be calculated to be 5ns). We set the CL to 2.5 in the motherboard BIOS, the total delay time = 6nsX2.5+6ns=21ns, and if the CL is set to 2, then the total delay time = 6nsX2+6ns=18ns, which is reduced by 3ns time.
From the perspective of the total delay time, the size of the CL value plays a key role. So users who have high system requirements and like overclocking usually like to buy memory with a lower CL value. At present, in addition to improving the performance of DDR by increasing the memory clock frequency, various memory particle manufacturers have considered to further reduce the CAS delay time to improve the memory performance.
However, it is not that the lower the CL value, the better the performance, because other factors will affect this data. For example, the high-speed caches of new-generation processors are more efficient, which means that the processors seldom read data directly from the memory. Furthermore, column data will be accessed more often, so the probability of occurrence of RAS-to-CAS is also high, and the time to read will also increase. Finally, it sometimes happens that a large amount of data is read at the same time. In this case, adjacent memory data will be read out at once, and the CAS delay time will only occur once.
Actual suggestion
When choosing to buy memory, it is best to choose memory with the same CL setting, because memory of different speeds is mixed in the system, and the system will run at a slower speed , That is, when the memory of CL2.5 and CL2 is inserted into the host at the same time, the system will automatically make both of them work in the CL2.5 state, causing a waste of resources.