1. Customized
ASIC is divided into all custom and semi-customized. The full-custom design requires designers to complete all circuit design, so there is a large amount of manpower and good flexibility but the development efficiency is low. If the design is ideal, the full customization can run faster than the half-custom ASIC chip. The semi-customized standard logic unit (Standard Cell) can be selected from the standard logic unit, MSI (such as adder, comparator, etc.), data path (such as ALU, Memory, Bus) from the standard logic cell. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Modern ASIC often contains the entire 32-bit processor, similar to the memory cells and other modules similar to ROM, RAM, EEPROM, FLASH. Such ASIC is often referred to as SOC (on-chip system).
FPGA is the close relative of ASIC, generally through the schematic, VHDL to model digital system, using EDA software simulation, synthesize, generates a network table based on some standard libraries, configured to the chip to use. Its difference between the ASIC is that the user does not need to intervene the layout wiring and process issues of the chip, and the logic function can be changed at any time and flexible.
2. Design
ASIC's design method and means have experienced decades of development evolution, from the initial hand-wide design to the process of advanced automatic implementation. This is also the result of science and technology, especially electronic information technology in recent decades. From the process of evolving from design, design means experienced manual design, computer-aided design (ICCAD), electronic design automation EDA, electronic system design automation ESDA, and user field programmable phase. The integrated circuit is made on the original silicon wafer having only a few hundred micron thick, each silicon can accommodate hundreds or even thousands of die. The transistors and connecting lines in the integrated circuit may be composed of many layers, and the current most complex process is approximately a diffusion layer or ion implantation layer located inside the silicon wafer, and 6 layers located on the surface of the wafer. composition. In terms of design methods, the method of designing integrated circuits can be divided into three ways to design, semi-customized, and programmable IC design.
2.1 Pixabine Design
All custom ASIC is the most basic design method of integrated circuit (without using existing library units), performing fine work for all components in integrated circuits Design method. The full-scale design can minimize the smallest area, the best wiring layout, the optimal power consumption volume, to obtain the best electrical characteristics. This method is particularly suitable for an analog circuit, a digital-to-analog mixing circuit, and a special requirement of speed, power consumption, dielectric area, other device characteristics (such as linearity, symmetry, current capacity, withstand voltage, etc.); or Outcoats in an existing component library. Features: Seiko, high design requirements, long cycle, expensive design cost.
Due to the plurality of unit libraries and function module circuits, the method of full design is gradually being replaced by the semi-customization method. In the current IC design, the entire circuit uses a phenomenon that is fully designed. All custom design requirements: The full-custom design should consider process conditions, depending on the complexity and difficulty determination of the circuit, the number of wiring layers, material parameters, process methods, limit parameters, and finished rates. Experiences and techniques are required, mastering various design rules and methods, generally completed by professional micro-electronic IC designers; conventional design can learn from previous design, some devices need to be designed separately according to electrical characteristics; layout, wiring, typographic combination, etc. Consider the design of the design principle design principle according to the optimal size, the most reasonable layout, the shortest connection, the most convenient pin. The layout design is related to the process, and it is necessary to fully understand the process specification, and reasonable design layout and processes according to process parameters and process requirements.
2.2 semi-custom design method
The semi-custom design method is also divided into a standard unit based design method and a door array design method.
The design method based on the standard unit is: a logical unit called a standard unit, such as with the door, or doors, multiplexing, triggers, etc., in accordance with certain specific rules , Form an ASIC with a pre-designed large unit. ASIC based on standard units is also known as CBIC (Cell-based IC).
The design method based on the gate array is to complete a dedicated integrated circuit design in a pre-formulated substrate or master on the matrix of transistor arrays. Half customization can shorten the development cycle, reduce development costs and risks.
1 ) Based on the design method of standard unit
This method adopts a pre-designed logic unit called standard unit. Such as gate circuits, multi-channel switches, triggers, clock generators, etc., arrange them into arrays in a particular rule, made semiconductor gate array, and subsequent, then subproplivers according to circuit functions and requirements Connect the desired logic unit into the desired dedicated integrated circuit. All standard units in the
unit library are pre-designed with custom methods, just like a wooden or wall, usually arranged, and leave a width wiring channel in accordance with the equidistant principle. . The main advantage of CBIC, the disadvantages:
Complete the ASIC design task with a pre-design, pre-test, predetermined standard unit library, saving money, and less risk.
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Designers only need to determine the layout of the standard unit and interconnection in CBIC.
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The standard unit can be placed anywhere in the chip.
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All mask layers are customized.
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can be embedded in the built-in functional unit.
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The manufacturing cycle is shorter, and the development cost is not too high.
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requires money to purchase or design standard cell libraries; ※ It is necessary to spend more time for the interconnection design of the mask layer.
2 ) Based on the ASIC gate array
is to repeat the transistor as a minimum unit, form a substantially array, form a semiconductor gate array master or substrate, and then connect the desired logic unit according to the circuit function and required mask. The desired dedicated integrated circuit. ASIC is designed with a gate array, only the metal layer used as the transistor interconnects is determined by the designer with a full-scale mask method, which is called masked gate array. The logic unit in the gate array is called a macro unit, where each of the basic unit layout of each logic unit is the same, only the interconnection between the unit and the unit is customized. Customer designers can select pre-design and predetermined feature logic units or macro units from the gate array cell library to customize interconnect design. The gate array is mainly suitable for small batch digital circuit designs in the short development cycle and low development costs.
2.3 Programmable device ASIC design
programmable ASIC is another special branch of the development of the dedicated integrated circuit, which mainly uses programmable integrated circuits such as PROM, GAL, Programmable circuits or logical arrays such as PLD, CPLD, FPGAs to obtain ASIC. Its main feature is to directly provide software design programming, complete the ASIC circuit function, and do not need to be processed by integrated circuit craft line.
The ASIC design species of programmable devices can accommodate different needs. The PLD and FPGA are used to compare the programmable device. Suitable for short development cycles, there is a certain complexity and digital circuit design of the circuit scale. Especially suitable for engineers engaged in electronic system design using EDA tools for ASIC design.
3. Cost review
ASIC design needs to reduce the design cost according to circuit function and performance requirements, select circuit form, device structure, process schedule, design rules, minimize the chip area, reduce design costs , Shorten the design cycle, and finally designed the correct, reasonable mask layout, and get the desired integrated circuit by the platelet and process flow.
From an economical point of view, ASIC's design requirement is a successful ASIC product with a minimum design cost in the lowest design cycle as short as possible. However, due to the different design methods of the ASIC, its design costs are different.
The complete design cycle is the longest design cycle, the design cost is expensive, the design cost is the highest, suitable for occasion of bulk is large or not for product cost.
The semi-custom design cost is lower than the full customization, but is higher than the programmable ASIC, suitable for large batch ASIC design.
Using the FPGA design of ASIC is the lowest design cost, but the chip is the highest, suitable for small batch ASIC products.
Most of the ASIC design is done in semi-custom and FPGA. Half-made and FPGA programmable ASIC-designed component cost comparison: CBIC components cost IC price 2-5 times. But the semi-custom ASIC must win in quantity, whether the design cost is much greater than the design cost of FPGA. ASIC design is not only considering the cost of component cost, the batch size of the ASIC element, the length of the production cycle, product profits, product life, etc. are also an important factor in which design methods, production processes, and cost restrictions.